1. Field of the Invention
The present invention generally relates to a clock duty ratio correction circuit for maintaining a clock signal to have a duty ratio of 1:1, and more specifically, to a clock duty ratio correction circuit for electrically converting an internal clock signal and then generating the internal clock signal having a predetermined duty ratio of 1:1 regardless of an externally applied clock signal by using a level difference of the converted electrical signal.
2. Description of the Prior Art
It is important to precisely control a duty ratio of a clock signal in a semiconductor device for inputting/outputting data by using the clock signal.
In generally, a clock signal having a duty ratio of 50% has been widely used in a digital clock application field such as a semiconductor integrated circuit. The 50% duty ratio means that a high level of the clock signal is the same as a low level of the clock signal.
Therefore, a duty ratio correction circuit is used to generate a clock signal having a duty ratio of 50% in a semiconductor device. If the duty ratio correction circuit receives a clock signal having other duty ratio except 50%, it converts the clock signal to have a duty ratio of 50%.
FIG. 1 is a block diagram of a clock duty ratio correction circuit disclosed in the U.S. Pat. No. 6,518,809. FIG. 2 is a detailed circuit diagram of FIG. 1.
The clock duty ratio correction circuit comprises a high pulse to charge converter 11, a low pulse to charge converter 12, a charge differencer 13, a digital converter logic 14 and a decoder 15.
The pulse to charge converters 11 and 12 convert a high level pulse width and a low level pulse width of a clock signal CLK_OUT outputted from a clock driving circuit (not shown) into a voltage level, respectively. The clock signal converted into a voltage level is compared with a reference voltage VREF previously set in the charge differencer 13. The charge differencer 13 generates driving signals START and STOP in response to the comparison result to drive the digital converter logic 14. The digital converter logic 14 performs a binary counting operation in response to the driving signals START and STOP, and outputs a counting signal having a plurality of bits to the decoder 15. The decoder 15 outputs a control signal PU/UD for correcting a duty ratio of the clock signal CLK_OUT depending on a counting value to the clock driving circuit (not shown). The control signal PU/PD turns on/off a PU/PD MOS (not shown) of the clock driving circuit, and controls the clock signal CLK_OUT to have its duty ratio of 50%.
The conventional clock duty ratio correction circuit regulates the duty ratio by controlling the size of MOS transistors in the clock driving unit for generating a clock signal. However, the method of controlling the size of MOS transistors has degraded correction resolution, and its use is improper in a system for receiving a differential clock signal.
In addition, the clock duty ratio correction circuit of FIG. 1 has more comparison errors than a direct comparison method since it compares output voltages of the pulse to charge converters 11 and 12 with the previously set reference voltage. Also, the clock duty ratio correction circuit of FIG. 1 has large power consumption because it uses two comparators for voltage comparison as shown in FIG. 2.